A New LSI Performance Prediction Model for Interconnection Analysis of Future LSIs
نویسندگان
چکیده
As the interconnection delays control the LSI performance, the LSI performance estimation at higher design level becomes more difficult. In this paper a new LSI performance model for the estimation is described, which is made up by adopting a new clock-skew model to the SUSPENS (Stanford University System Performance Simulator) model. Using the model, it is cleared that a specific block size, where the line delay overcomes the block cycle time, becomes shorter as the LSI generation proceeds.
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